As critical dimensions (CD) of ICs shrink, the metal fill in a RMG process becomes difficult. The RMG process requires forming a gate opening in a dielectric layer and filling the gate opening with gate materials. As gate dimensions shrink, the gate opening may be inadequate to fill such that the metal pinches off, thereby resulting in high gate resistance.
Advanced nodes are now employing one or more recesses of either gate work function material (WFM), gate metal fill, or gate spacer and dielectric gap fill over the gates to enable placing the source/drain (S/D) contacts in close proximity for technology scaling. However, the above schemes add new process challenges to control final gate heights across different gate widths (viz. short vs. long) and multi-threshold voltage (Vt) architectures. Some common issues include high-K damage and WFM loss over the gate fin and final gate height inconsistencies, leading to varying self-aligned contact (SAC) cap budgets, which can cause S/D to gate electrode shorts resulting in device performance degradation.
A need therefore exists for methodology enabling improved metal fill and gate height control across short and long channel lengths or gate widths, and the resulting device.